Conventional latch integrated circuits frequently utilize inverters coupled in antiparallel to provide a data latching operation. When utilized in synchronous integrated circuits, this latching operation may be synchronized with a timing signal, such as a clock signal (CLK). One example of a conventional latch integrated circuit includes a pulse latch, which utilizes a write enable pulse of sufficient “fixed” width to perform a write operation. Unfortunately, changes in performance of a pulse latch caused by changes in fabrication process, voltage and/or operating temperature (i.e., PVT changes) may cause fixed duration write operations to become unreliable by providing insufficient time for accurate loading of new data into the pulse latch. Examples of conventional latch integrated circuits are disclosed in U.S. Pat. No. 6,760,263 to Liou, entitled “Method and Device for Controlling Data Latch Time”; U.S. Pat. No. 6,115,322 to Kanda et al., entitled “Semiconductor Device Accepting Data Which Includes Serial Data Signals, in Synchronization with a Data Strobe Signal”; and U.S. Pat. No. 7,411,413 to Shimazaki et al., entitled “Pulse Latch Circuit and Semiconductor Integrated Circuit.”